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w25q128bv publication release date: october 03 , 201 3 - 1 - revision h 3v 12 8m - bit serial flash memory with dual and quad spi
w25q128bv - 2 - table of contents 1. general description ................................ ................................ ................................ ............... 5 2. features ................................ ................................ ................................ ................................ ....... 5 3. package types and pi n configurations ................................ ................................ .......... 6 3.1 pad configuration wson 8x6 - mm ................................ ................................ ...................... 6 3.2 pad description wson 8x6 - mm ................................ ................................ .......................... 6 3.3 pin configuration soic 300 - mil ................................ ................................ ........................... 7 3.4 pin description s oic 300 - mil ................................ ................................ ............................... 7 3.5 ball configuration tfbga 8x6 - mm (5x5 or 6x4 ball array) ................................ ................. 8 3.6 ball description tfbga 8x6 - mm ................................ ................................ ......................... 8 4. pin descriptions ................................ ................................ ................................ ........................ 9 4.1 chip select (/cs) ................................ ................................ ................................ .................. 9 4.2 serial data input, output and ios (di, do and io0, io1, io2, io3) ................................ .... 9 4.3 write protect (/wp) ................................ ................................ ................................ ............... 9 4.4 hold (/hold) ................................ ................................ ................................ ..................... 9 4.5 serial clock (clk) ................................ ................................ ................................ ................ 9 5. block diagram ................................ ................................ ................................ .......................... 10 6. functional descripti ons ................................ ................................ ................................ ..... 11 6.1 spi operations ................................ ................................ ................................ ............. 11 6.1.1 standard spi instructions ................................ ................................ ................................ ..... 11 6.1.2 dual spi instructions ................................ ................................ ................................ ............ 11 6.1.3 quad spi instructions ................................ ................................ ................................ .......... 11 6.1.4 hold function ................................ ................................ ................................ ....................... 11 6.2 write protection ................................ ................................ ................................ ....... 12 6.2.1 write protect features ................................ ................................ ................................ ......... 12 7. status registers and instructions ................................ ................................ ............... 13 7.1 status registers ................................ ................................ ................................ ........ 13 7.1.1 busy status (busy) ................................ ................................ ................................ ........... 13 7.1.2 write enable latch status (wel) ................................ ................................ ......................... 13 7.1.3 block protect bits (bp2, bp1, bp0) ................................ ................................ ...................... 13 7.1.4 top/bottom block protect bit (tb) ................................ ................................ ........................ 13 7.1.5 sector/block protect bit (sec) ................................ ................................ ............................. 13 7.1.6 complement protect bit (cmp) ................................ ................................ ............................ 14 7.1.7 status register protect bits (srp 1, srp0 ) ................................ ................................ .......... 14 7.1.8 erase/program suspend status (sus) ................................ ................................ ................ 14 7.1.9 security register lock bits (lb3, lb2, lb1) ................................ ................................ ........ 14 7.1.10 quad enable bit ( qe ) ................................ ................................ ................................ ......... 15
w25q128bv publication release date: october 03 , 201 3 - 3 - revision h 7.1.11 status register memory protection (cmp = 0) ................................ ................................ ... 16 7.1.12 st atus register memory protection (cmp = 1) ................................ ................................ ... 17 7.2 instructions ................................ ................................ ................................ ................. 18 7.2.1 manufacturer and device identification ................................ ................................ ................ 18 7.2.2 instruction set table 1 (erase, program instructions) ( 1 ) ................................ ....................... 19 7.2.3 instruction set table 2 (read instructions) ................................ ................................ .......... 20 7.2.4 instruction set table 3 (id, security instructions) ................................ ................................ 21 7.2.5 write enable (06h) ................................ ................................ ................................ ............... 22 7.2.6 write enable for volatile status register (50h) ................................ ................................ .... 22 7.2.7 write disable (04h) ................................ ................................ ................................ ............... 23 7.2.8 read status register - 1 (05h) and re ad status register - 2 ( 3 5h) ................................ ......... 24 7.2.9 write status register (01h) ................................ ................................ ................................ .. 24 7.2.10 read data (03h) ................................ ................................ ................................ ................. 26 7.2.11 fast read (0bh) ................................ ................................ ................................ ................. 27 7.2.12 fast read dual output (3bh) ................................ ................................ ............................. 28 7.2.13 fast read quad output (6bh) ................................ ................................ ............................ 29 7.2.14 f ast read dual i/o (bbh) ................................ ................................ ................................ ... 30 7.2.15 fast read quad i/o (ebh) ................................ ................................ ................................ . 32 7.2.16 word read quad i/o (e7h) ................................ ................................ ................................ 34 7.2.17 octal word read quad i/o (e3h) ................................ ................................ ....................... 36 7.2.18 set burst with wrap (77h) ................................ ................................ ................................ .. 38 7.2.19 continuous read mode bits (m7 - 0) ................................ ................................ ................... 39 7.2.20 continuous read mode reset (ffh or ffffh) ................................ ................................ .. 39 7.2.21 page program (02h) ................................ ................................ ................................ ........... 40 7.2.22 quad input page program ( 3 2h) ................................ ................................ ........................ 41 7.2.23 sector erase (20h) ................................ ................................ ................................ ............. 42 7.2.24 32kb block erase (52h) ................................ ................................ ................................ ..... 43 7.2.25 64kb block erase (d8h) ................................ ................................ ................................ ..... 44 7.2. 26 chip erase (c7h / 60h ) ................................ ................................ ................................ ....... 45 7.2.27 erase / program suspend (75h) ................................ ................................ ......................... 46 7.2.28 erase / program resume (7ah) ................................ ................................ ......................... 47 7.2.29 power - down (b9h) ................................ ................................ ................................ .............. 48 7.2.30 release power - down / device id (abh) ................................ ................................ ............. 49 7.2.31 rea d manufacturer / device id (90h) ................................ ................................ ................. 51 7.2.32 read manufacturer / device id dual i/o (92h) ................................ ................................ ... 52 7.2.33 read manufacturer / device id quad i/o (94h) ................................ ................................ . 53 7.2.34 read unique id number (4bh) ................................ ................................ .......................... 54 7.2.35 read jedec id (9fh) ................................ ................................ ................................ ........ 55 7.2.36 read sfdp register (5ah) ................................ ................................ ................................ 56 7.2.37 erase security registers (44h) ................................ ................................ ........................... 57 7.2.38 program security regist ers (42h) ................................ ................................ ...................... 58
w25q128bv - 4 - 7.2.39 read security registers (48h) ................................ ................................ ........................... 59 8. electrical character istics ................................ ................................ .............................. 60 8.1 absolute maximum ratings (1) (2) ................................ ................................ ...................... 60 8.2 operating ranges ................................ ................................ ................................ .............. 60 8.3 power - up timing and write inhibit thres hold ( 1 ) ................................ ............................... 61 8.4 dc electrical characteristics ................................ ................................ .............................. 62 8.5 ac measurement conditions ................................ ................................ ............................. 63 8.6 ac electrical characteristics ................................ ................................ .............................. 64 8.7 ac electrical characteristics (contd) ................................ ................................ ................. 65 8.8 serial output timing ................................ ................................ ................................ ........... 66 8.9 serial input timing ................................ ................................ ................................ .............. 66 8.10 hold timing ................................ ................................ ................................ ...................... 66 8.11 wp timing ................................ ................................ ................................ .......................... 66 9. package spec ification ................................ ................................ ................................ .......... 67 9.1 8 - pad wson 8x6 - mm (package code e) ................................ ................................ ......... 67 9.2 16 - pin soic 300 - mil (package code f) ................................ ................................ ............ 68 9.3 24 - ball tfbga 8x6 - mm (package code b, 5x5 - 1 ball array) ................................ ........... 69 9.4 24 - ball tf bga 8x6 - mm (package code c, 6x4 ball array) ................................ .............. 70 10. ordering information ................................ ................................ ................................ .......... 71 10.1 valid part numbers and top side marking ................................ ................................ ........ 72 11. revision history ................................ ................................ ................................ ...................... 73
w25q128bv publication release date: october 03 , 201 3 - 5 - revision h 1. general description the w25q128b v ( 1 28 m - bit) serial flash memory provide s a storage solution for systems with limited space, pins and power . the 25 q series offers flexibility and performance well beyond ordinary serial flash devices. they are ideal for code shadowing to ram, executing code directly from d ua l/quad spi (xip ) and storing voice, text and data. the device operate s on a single 2.7v to 3.6v power supply with current consumption as low as 4ma active and 1a for power - down. the w25q128b v array is organized into 65,53 6 programmable pages of 256 - bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 ( 4kb sector erase), groups of 128 (32kb block erase), groups of 256 ( 64kb block erase) or the entire chip (chip erase). the w25q128b v has 4,09 6 erasable sectors and 25 6 erasable blocks respectively. the small 4kb sectors allow for greater flexibility in a pplications that require data and parameter storage. (see figure 2.) the w25q128b v supports the standard serial peripheral interface (spi), and a high performance d ual /quad output as well as dual/quad i/o spi: serial clock, chip select, serial data i/o 0 ( di), i/o1 (do), i/o2 (/wp), and i/o3 (/hold) . spi clock frequencies of up to 104 mhz are supported allowing equivalent clock rates of 208 mhz (104mhz x 2) for dual output and 280 mhz ( 70 mhz x 4 ) for quad spi when using the fast rea d quad spi instruction s . the se transfer rates can out p erform standard asynchronous 8 and 16 - bit parallel flash memories. the continuous read mode allows for efficient memory access with as few as 8 - clocks of instruction - overhead to read a 24 - bit address, allowing true xip ( execute in place) operation. a hold pin, write protect pin and programmable write protect ion , with top, bottom or complement array control, provide further control flexibility. additionally, the device supports jedec standard manufacturer and device identification w ith a 64 - bit unique serial number . 2. features ? family of spiflash memories C w25q128bv: 128m - bit/16m - byte C 256 - byte per programmable page C standard spi: clk, /cs, di, do, /wp, /hold C dual spi: clk, /cs, io 0 , io 1 , /wp, /hold C quad spi: clk, /cs, io 0 , io 1 , io 2 , io 3 ? highest performance serial flash C 104/70mhz dual output/quad spi clocks C 208/280mhz equivalent dual /quad spi C 35mb/s continuous data transfer rate C up to 5x that of ordinary serial flash C more than 100,000 erase/program cycles (1) C more tha n 20 - year data retention ? efficient continuous read mode C low instruction overhead C continuous read with 8/16/32/64 - byte wrap C as few as 8 clocks to address memory C allows true xip (execute in place) operation C outperforms x16 parallel flash ? low powe r, wide temperature range C single 2. 7 to 3.6v supply C 4ma active current, <1a power - down current C - 40c to +85c operating range ? flexible architecture with 4kb sectors C uniform sector/block erase (4k/32k/64k - byte) C program one to 256 bytes C erase/pr ogram suspend & resume ? advanced security features C software and hardware write - protect C top/bottom, 4kb complement array protection C lock - down and otp array protection C 64 - bit unique serial number for each device C discoverable parameters (sfdp) regist er C 3x256 - byte security registers with otp locks C volatile & non - volatile status register bits ? space efficient packaging C 8 - pad wson 8x6 - mm C 16 - pin soic 300 - mil C 24 - ball tfbga 5x5 - mm & 8x6 - mm C contact winbond for kgd and other options
w25q128bv - 6 - 3. package type s and pin configurat ions w25q128bv is offered in an 8 - pad wson 8x6 - mm (package code e), a 16 - pin soic 300 - mil (package code f) and two 24 - ball 8x6 - mm tfbga s (package code b, c) as shown in figure 1a - c respectively. package diagrams and dimensions are illus trated at the end of this datasheet. 3.1 p ad configuration wson 8x6 - mm figure 1 a . w25q128b v pad assignments, 8 - pad wson 8 x 6 - mm (package code e ) 3.2 p ad description wson 8 x 6 - mm pad no. p ad name i/o function 1 /cs i chip select input 2 do ( io1 ) i/ o data output ( data input output 1)* 1 3 /wp ( io2 ) i /o write protect input ( data input output 2)* 2 4 gnd ground 5 di ( io0 ) i/o data i nput ( data input output 0)* 1 6 clk i serial clock input 7 /hold ( io3 ) i /o hold input ( data input output 3)* 2 8 vcc power supply *1 : io0 and io1 are used for standard and dual spi instructions *2 : io0 C io3 are used for quad spi instructions 1 2 3 4 /cs do (io 1 ) /wp (io 2 ) gnd vcc /hold (io 3 ) di (io 0 ) clk top view 8 7 6 5
w25q128bv publication release date: october 03 , 201 3 - 7 - revision h 3.3 pin configuration soic 300 - mil figure 1 b . w25q128b v pin assignments, 16 - pin soic 300 - mil (package code f) 3.4 pin description soic 300 - mil p in no. p in name i/o function 1 /hold ( io3 ) i /o hold input ( data input output 3)* 2 2 vcc power supply 3 n/c no connect 4 n/c no connect 5 n/c no connect 6 n/c no connect 7 /cs i chip select input 8 do (io1) i/ o data out put (data input output 1)* 1 9 /wp ( io2 ) i /o write protect input ( data input output 2)* 2 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no connect 15 di ( io0 ) i /o data input (data input output 0)* 1 16 clk i serial clock input *1: io0 and io1 are used for standard and dual spi instructions . *2: io0 C io3 are used for quad spi instructions, /wp or /hold functions are only available for standard/dual spi . 1 2 3 4 /cs do (io 1 ) /wp (io 2 ) gnd vcc /hold (io 3 ) di (io 0 ) clk top view nc nc nc nc nc nc nc nc 5 6 7 8 10 9 11 12 13 14 15 16
w25q128bv - 8 - 3.5 b all configuration tfbga 8x6 - mm (5x5 or 6x4 ball array) figure 1 c . w25q128b v ball assignm ents, 24 - ball tfbga 8x6 - mm (package code b, c ) 3.6 b all description tfbga 8x6 - mm ball no. p in name i/o function b2 clk i serial clock input b3 gnd ground b4 vcc power supply c2 /cs i chip select input c4 /wp ( io2 ) i /o write protect input ( data input out put 2)* 2 d2 do (io1) i/ o data out put (data input output 1)* 1 d3 di ( io0 ) i /o data input (data input output 0)* 1 d4 /hold ( io3 ) i /o hold input ( data input output 3)* 2 multiple nc no connect *1 : io0 and io1 are used for standard and dual spi instructio ns . *2 : io0 C io3 are used for quad spi instructions , /wp or /hold functions are only available for standard/dual spi. d 1 / h o l d ( i o 3 ) d i ( i o 0 ) d o ( i o 1 ) / w p ( i o 2 ) d 2 d 3 d 4 n c e 1 n c n c n c e 2 e 3 e 4 n c f 1 n c n c n c f 2 f 3 f 4 n c a 1 n c n c n c a 2 a 3 a 4 n c b 1 v c c g n d c l k b 2 b 3 b 4 n c c 1 n c / c s c 2 c 3 c 4 n c t o p v i e w p a c k a g e c o d e c d 1 / h o l d ( i o 3 ) d i ( i o 0 ) d o ( i o 1 ) / w p ( i o 2 ) d 2 d 3 d 4 n c e 1 n c n c n c e 2 e 3 e 4 n c b 5 n c n c n c a 2 a 3 a 4 n c b 1 v c c g n d c l k b 2 b 3 b 4 n c c 1 n c / c s c 2 c 3 c 4 n c t o p v i e w p a c k a g e c o d e b c 5 n c d 5 n c e 5 n c a 5 n c
w25q128bv publication release date: october 03 , 201 3 - 9 - revision h 4. pin descriptions 4.1 chip select ( /cs ) the spi chip select ( /cs ) pin enables and disables device operation. when /cs is high the device is d eselected and the serial data output ( do, or io0, io1, io2, i o3 ) pin s are at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power - up, /cs must transition from high to low before a new instruction will be accepted. t he /cs input must track the vcc supply level at power - up (see write protection and figure 3 8 ). if needed a pull - up resister on /cs can be used to accomplish this. 4.2 serial data input, output and ios (d i , d o and io0, io1, io2, io3) the w25q128b v support s s tandard spi, dual spi and quad spi operation. standard spi instructions use the unidirectional d i (input) pin to serially write instructions, addresses or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge of clk. dual and quad spi instruction s use the bidirectional io pins to serially write instructions, addresses or data to the device on the rising edge of clk and read data or status from the device on the falling edge of clk. quad spi instructions require the non - volatile quad enable bit (qe) in status register - 2 to be set. when qe=1 , the /wp pin becomes i o 2 and /hold pin becomes io3. 4.3 write protect ( /wp ) the write pro tect ( /wp ) pin can be used to prevent the status register from being written. used in conjunction with the status registers block protect ( cmp, sec , tb, bp2, bp1 and bp0 ) bits and status register protect (srp) bits, a portion as small as a 4kb sector or t he entire memory array can be hardware protected. the /wp pin is active low. when the qe bit of status register - 2 is set for q uad i/ o, the /wp pin function is not available since this pin is used for i o 2 . see figure 1a - c for the pin c onfiguration of quad i /o operation . 4.4 h old ( /hold ) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored (dont care). when / hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are sharing the same spi signals. the /hold pin is active low. when the qe bit of status register - 2 is set for quad i/o, the /hold pin function is not available since this pin is used for io3. see figure 1a - c for the pin configuration of quad i/o operation. 4.5 serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input an d output operations. ("see spi operations")
w25q128bv - 10 - 5. block di agram figure 2 . w25q128b v serial flash memory block diagram 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh column decode and 256 - byte page buffer beginning page address ending page address w25q128bv spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /hold (io 3 ) /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 1 - 3 write protect logic and row decode 000000h 0000ffh sfdp register 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 3fff00h 3fffffh ? block 63 (64kb) ? 3f0000h 3f00ffh 40ff00h 40ffffh ? block 64 (64kb) ? 400000h 4000ffh ? ? ? 7fff00h 7fffffh ? block 127 (64kb) ? 7f0000h 7f00ffh 80ff00h 80ffffh ? block 128 (64kb) ? 800000h 8000ffh ? ? ? ffff00h ffffffh ? block 255 (64kb) ? ff0000h ff00ffh 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh column decode and 256 - byte page buffer beginning page address ending page address w25q128bv spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /hold (io 3 ) /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 1 - 3 write protect logic and row decode 000000h 0000ffh sfdp register 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 3fff00h 3fffffh ? block 63 (64kb) ? 3f0000h 3f00ffh 40ff00h 40ffffh ? block 64 (64kb) ? 400000h 4000ffh ? ? ? 7fff00h 7fffffh ? block 127 (64kb) ? 7f0000h 7f00ffh 80ff00h 80ffffh ? block 128 (64kb) ? 800000h 8000ffh ? ? ? ffff00h ffffffh ? block 255 (64kb) ? ff0000h ff00ffh
w25q128bv publication release date: october 03 , 201 3 - 11 - revision h 6. functional descripti on s 6.1 spi operations 6.1.1 standard spi instructions the w25q128b v is accessed through an spi compatible bus consisting of four signals: serial clock (clk) , chip select ( /cs ), serial data input ( di ) and serial data output (do). standard spi instructions use the di input pin to serially write instructions, addresses or data to the device on the rising edge of clk . the do output pin is used to read data or sta tus from the device on the falling edge of clk. spi bus operation mode 0 (0, 0) and 3 (1, 1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 , the clk signal is normally low on the falling and rising edges of /cs. for mode 3 , the clk signal is normally high on the falling and rising edges of /cs . 6.1.2 dual spi instructions the w25q128b v support s dua l spi operation when using the fast read dual output (3bh) and fast read dual i/o (bbh) instruction s . th ese instructions allow data to be transferred to or from the device at two to three times the rate of ordinary serial flash devices. the dual spi re ad i nstruction s are ideal for quickly downloading code to ram upon power - up (code - shadowing) or for execut ing non - speed - critical code directly from the spi bus (xip) . when using dual spi instructions , the di and do pins become bidirectional i/ o pins: io0 a nd io1. 6.1.3 quad spi instructions the w25q128b v supports quad spi operation whe n using the fast read quad output (6bh) , fast read quad i/o (ebh) , word read quad i/o (e7h) and octal word read quad i/o (e3h) instructions . these instructions allow data to be transferred to or from the device six to eight times the rate of ordinary serial flash. the quad read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code - shadowing to ram or execut ion directly from the spi bus (xip) . when using quad spi instructions the di and do pins become bidirectional io0 and io1 , and the /wp and /hold pins become io2 and io3 respectively. quad spi instructions require the non - volatile quad enable bit (qe) in status register - 2 to be set . 6.1.4 hold function for standard spi and dual spi operations, t he /hold signal allows the w25q128b v operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases where the spi data and clock signa ls are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. the /hold function is only available for standard spi and dual spi operation, not during quad spi. to initiate a /hold condition, the device must be selected with /cs low. a /hold c ondition will activate on the falling edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the
w25q128bv - 12 - rising edge of th e /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, a nd serial data input (di ) and se rial clock (clk) are ignored. the chip select ( /cs ) signal should be kept active low for the full duration of the /hold operation to avoid resetting the internal logic state of the device. 6.2 write protection applications that use non - volatile memory must tak e into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern , the w25q128b v provides several means to protect the data from inadvertent writes. 6.2.1 write protect features ? device resets when vcc is below threshold ? time delay write disable after power - up ? write enable/disable instructions and a ut omatic write disable after e rase or program ? software and hardware (/wp pin) write protection using status register ? write protection using p ower - down instruction ? lock down write protection until next power - up ? one time program (otp) write protection * * note : this feature is available upon special order. please contact winbond for details . upon power - up or at power - down , the w25q128b v will ma intain a reset condition while vcc is below the threshold value of v wi , (see power - up timing and voltage levels and figure 3 8 ). while reset, all operations are disabled and no instructions are recognized. during power - up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page program, sector erase, block erase, chip erase and the write status register instructions. note that the chip select pin ( /cs ) must track the vcc supply level at power - up until the vcc - min level and t vsl time delay is reached. if needed a pull - up resister on /cs can be used to accomplish this. after power - up the device is automatically placed in a write - disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, block erase, chip erase or write status register instruction will be accepted. after completing a program, erase or write in struction the write enable latch (wel) is automatically cleared to a write - disabled state of 0. software controlled write protection is facilitated using the write status register instruction and setting the status register protect (srp 0, srp1 ) and block p rotect ( cmp, sec , tb , bp2, bp1 and bp0 ) bits. these settings allow a portion as small as 4kb sector or the entire memory array to be configured as read only. used in conjunction with the write protect ( /wp ) pin, changes to the status register can be enable d or disabled under hardware control. see status register section for further information. additionally, the power - down instruction offers an extra level of write protection as all instructions are ignored except for the release power - down instruction.
w25q128bv publication release date: october 03 , 201 3 - 13 - revision h 7. st atus register s and instructions the read status register - 1 and status register - 2 instruction s can be used to provide status on the availability of the flash memory array, if the device is write enabled or disabled, t he state of write protection , quad spi s e tting , security register lock status and erase/program suspend status . the write status register instruction can be used to configure the device write protection features , quad spi sett i ng and security register otp lock . write access to the status registe r is controlled by the state of the non - volatile s tatus register protect bits (srp 0, srp1 ) , the write enable instruction, and during standard/dual spi operations, the /wp pin . 7.1 status register s 7.1.1 busy status (busy) busy is a read only bit in the status regis ter (s0) that is set to a 1 state when the device is executing a page program, quad page program, sector erase, block erase, chip erase, write status register or erase/program security register instruction. during this time the device will ignore further i nstructions except for the read status register and erase /program suspend instruction (see t w , t pp , t se , t b e , and t c e in ac characteristics). when the program, erase or write status /security register instruction has completed, the busy bit will be cleared to a 0 state indicating the device is ready for further instructions. 7.1.2 write enable latch status (wel) write enable latch (wel) is a read only bit in the statu s register (s1) that is set to 1 after executing a write enable instruction. th e wel status bit i s cleared to 0 when the device is write disabled. a write disable state occurs upon power - up or after any of the following instructions: write disable, page program, quad page program, sector erase, block erase, chip erase, write status register , erase sec urity register and program security register . 7.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, bp0 ) are non - volatile read/write bits in the status register (s4, s3, and s2 ) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the factory default setting for the block protection bits is 0, none of the array protected. 7.1.4 top/bottom block protect bit (tb) the non - volatile top/bottom bit (tb) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the arra y as shown in the status register memory protection table. the f actory default setting is tb=0. the tb bit can be set with the write status register instruction depending on the state of the srp0, srp1 and wel bits. 7.1.5 sector /block protect bit (sec) the non - volatile sector /block p rotect bit (sec) controls if the block protect bits (bp2, bp1, bp0) protect either 4kb sectors (sec=1) or 64kb blocks (sec=0) in the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection tabl e. the default setting is sec =0.
w25q128bv - 14 - 7.1.6 complement protect bit (cmp) the c omplement p rotect bit (cmp) is a non - volatile read/write bit in the status register (s14). it is used in conjunction with sec, tb, bp2, bp1 and bp0 bits to provide more flexibility for the array protection. once cmp is set to 1, previous array protection set by sec, tb, bp2, bp1 and bp0 will be reversed. for instance, when cmp=0, a top 4kb sector can be protected while the rest of the array is not; when cmp=1, the top 4kb sector will become unprotected while the rest of the array become read - only. please refer to the status register memory protection table for details. the default setting is cmp =0. 7.1.7 status register protect bits (srp 1 , srp 0 ) the status register protect bits (srp 1 and srp0 ) are non - volatile read/write bits in the status register ( s8 and s7). the srp bits control the method of write protection: s oftware p rotection, h ardware p rotection, p ower s upply l ock - d own or o ne t ime p rogrammable (otp) p rotection. srp1 srp0 /wp status register description 0 0 x software protection /wp pin has no control. the status register can be written to after a write enable instruction , wel=1 . [factory default] 0 1 0 hardware protect ed when /wp pin is low the status register locked and can not be writte n to . 0 1 1 hardware unprotected when /wp pin is high the status register is unlocked and can be written to after a write enable instruction , wel=1. 1 0 x power supply lock - down status register is protected and can not be written to again until the nex t power - down , power - up cycle . ( 1 ) 1 1 x one time program ( 2 ) status register is permanently protected and can not be written to. note: 1. when srp1, srp0 = (1, 0), a power - down, power - up cycle will change srp1, srp0 to (0, 0) state. 2 . this feature is av ailable upon special order. please contact winbond for details. 7.1.8 erase/program suspend status (sus) the suspend status bit is a read only bit in the status register (s15) that is set to 1 after executing an erase/program suspend (75h) instruction. the sus s tatus bit is cleared to 0 by erase/program resume (7ah) instr uction as well as a power - down, power - up cycle. 7.1.9 security register lock bits (lb3, lb2, lb1 ) the security register lock bits (lb3, lb2, lb1) are non - volatile one time program (otp) bits in status register (s13, s12, s11) that provide the write protect control and status to the security registers . the default state of lb [3:1] is 0, securi ty registers are unlocked. lb[3:1] can be set to 1 individually using the write status register instruction. lb[3 :1] are one time programmable (otp), once its set to 1, the corresponding 256 - byte security register will become read - only permanently.
w25q128bv publication release date: october 03 , 201 3 - 15 - revision h 7.1.10 quad enable bit ( qe ) the quad enable (qe ) bit is a non - volatile read/write bit in the status register (s 9 ) that allow s quad spi operation . when the qe bit is set to a 0 state (factory default) , the /wp pin and /h old pin are enabled . when the qe bit is set to a 1 , the quad io2 and i o3 pins are enabled , and /wp and /hold functions are disabled. warning: i f the /wp or /hold p ins are tied directly to the power supply or ground during standard spi or dual spi operation , t he qe bit should never be set to a 1 . figure 3 a . status register - 1 figure 3 b . status register - 2 s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non - volatile) sector protect (non - volatile) top/bottom protect (non - volatile) block protect bits (non - volatile) write enable latch erase/write in progress s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non - volatile) sector protect (non - volatile) top/bottom protect (non - volatile) block protect bits (non - volatile) write enable latch erase/write in progress s15 s14 s13 s12 s11 s10 s9 s8 sus cmp lb3 lb2 lb1 (r) qe srp1 suspend status complement protect (non - volatile) security register lock bits (non - volatile otp) quad enable (non - volatile) status register protect 1 (non - volatile) reserved s15 s14 s13 s12 s11 s10 s9 s8 sus cmp lb3 lb2 lb1 (r) qe srp1 suspend status complement protect (non - volatile) security register lock bits (non - volatile otp) quad enable (non - volatile) status register protect 1 (non - volatile) reserved
w25q128bv - 16 - 7.1.11 status register memory pr otection (cmp = 0) status register (1) w25q128bv (128m - bit) memory protecti on (3) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 none none none none 0 0 0 0 1 252 thru 255 f c0000h C f fffffh 25 6kb upper 1/64 0 0 0 1 0 248 thru 255 f8 0000h C f fffffh 512kb upper 1/32 0 0 0 1 1 240 thru 255 f0 0000h C f fffffh 1mb upper 1/16 0 0 1 0 0 224 thru 255 e 00000h C f fffffh 2mb upper 1/8 0 0 1 0 1 192 thru 255 c 00000h C f fffffh 4mb upper 1/4 0 0 1 1 0 12 8 thru 255 8 00000h C f fffffh 8mb upper 1/2 0 1 0 0 1 0 thru 3 000000h C 03ffffh 256kb lower 1/64 0 1 0 1 0 0 thru 7 000000h C 07ffffh 512kb lower 1/32 0 1 0 1 1 0 thru 15 000000h C 0fffffh 1mb lower 1/16 0 1 1 0 0 0 thru 31 000000h C 1fffffh 2mb lower 1/8 0 1 1 0 1 0 thru 63 000000h C 3fffffh 4mb lower 1/4 0 1 1 1 0 0 thru 127 000000h C 7 f ffffh 8mb lower 1/2 x x 1 1 1 0 thru 255 000000h C ffffffh 16mb all 1 0 0 0 1 255 f ff000 h C f f ffffh 4kb u - 1/4096 1 0 0 1 0 255 f fe000 h C f f ffffh 8kb u - 1/2048 1 0 0 1 1 255 f fc000 h C f f ffffh 16kb u - 1/1024 1 0 1 0 x 255 f f8000 h C f f ffffh 32kb u - 1/512 1 1 0 0 1 0 000000h C 000fffh 4kb l - 1/4096 1 1 0 1 0 0 000000h C 001fffh 8kb l - 1/2048 1 1 0 1 1 0 000000h C 003fffh 16kb l - 1/1024 1 1 1 0 x 0 000 000h C 007fffh 32kb l - 1/512 note s : 1. x = dont care 2. l = lower; u = upper 3. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
w25q128bv publication release date: october 03 , 201 3 - 17 - revision h 7.1.12 status register memory protection (cmp = 1) status register (1) w25q128bv (128m - bit) memory protecti on (3) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 0 thru 255 000000h - ffffffh 16mb all 0 0 0 0 1 0 thru 251 000000h - f bff ff h 16 ,12 8kb lower 63/64 0 0 0 1 0 0 thru 247 000000h C f7ffffh 15,872kb lower 31/32 0 0 0 1 1 0 thru 239 000000h - efffff h 15 mb lower 15/16 0 0 1 0 0 0 thru 223 000000h - dfffffh 14mb lower 7/8 0 0 1 0 1 0 thru 191 000000h - bfffffh 12 mb lower 3/4 0 0 1 1 0 0 thru 127 000000h - 7fffffh 8 mb lower 1/2 0 1 0 0 1 4 thru 255 040000h - ffffffh 16 ,128kb upper 63/64 0 1 0 1 0 8 thru 255 080000h - ffffffh 15,872kb upper 31/32 0 1 0 1 1 16 thru 255 100000h - ffffffh 15 mb upper 15/16 0 1 1 0 0 32 thru 255 200000h - f fffffh 14mb upper 7/8 0 1 1 0 1 64 thru 255 400000h - ffffffh 12 mb upper 3/4 0 1 1 1 0 128 thru 255 800000h - ffffffh 8 mb upper 1/2 x x 1 1 1 none none none none 1 0 0 0 1 0 thru 25 5 000 000 h C f f efffh 16 ,380kb l - 4095/4096 1 0 0 1 0 0 thru 25 5 000 000 h C f f dfffh 16 ,376kb l - 2047/2048 1 0 0 1 1 0 thru 25 5 000 000 h C f f bfffh 16 ,368kb l - 1023/1024 1 0 1 0 x 0 thru 25 5 000 000 h C f f 7fffh 16 ,352kb l - 511/512 1 1 0 0 1 0 thru 255 00 1 000h C fff fffh 16 ,380kb u - 4095/4096 1 1 0 1 0 0 thru 255 00 2 000h C f ff fffh 16 ,376kb u - 2047/2048 1 1 0 1 1 0 thru 255 00 4 000h C fff fffh 16 ,368kb u - 1023/1024 1 1 1 0 x 0 thru 255 00 8 000h C fff fffh 16 ,352kb u - 511/512 note s : 1. x = dont care 2. l = lower; u = upper 3. if any erase or program command specifies a memor y region that contains protected data portion, this command will be ignored.
w25q128bv - 18 - 7.2 instructions the instruction set of the w25q128b v consists of thirty f ive basic instructions that are fully controlled through the spi bus (see instruction set table 1 - 3 ). instr uctions are initiated with the falling edge of chip select (/cs) . the first byte of data clo cked into the di input provides the i nstruction code. data on the di input is sampled on the rising edge of clock with most significant bit (msb) first. instructio ns vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (dont care), and in some cases, a combination. instructions are completed with the rising edge of edge /cs . clock relative timing diagrams for each instruction are included in figure s 4 through 3 7 . all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary ( / cs driven high after a full 8 - bits have been clocked) otherwise the instruction will be ignor ed. this feature further protects the device from inadvertent writes. additionally, while the memory is being programmed or erased, or when the status register is being written, all instructions except for re ad status register will be ignored until the program or erase cycle has completed. 7.2.1 manufacturer and device identification manufacturer id (m f 7 - m f 0) winbond serial flash ef h device id (id7 - id0) (id15 - id0) instruction abh, 90h , 92h, 94h 9fh w25q128 b v 1 7 h 401 8 h
w25q128bv publication release date: october 03 , 201 3 - 19 - revision h 7.2.2 instruction set table 1 (erase, program instructions) ( 1 ) instruction name byte 1 ( code ) byte 2 byte 3 byte 4 byte 5 byte 6 write enable 06h write enable for volatile status register 50h write disable 04h read status register - 1 05h (s7 C s0) ( 2 ) read status register - 2 35h (s 15 C s 8 ) ( 2 ) write status register 01h s7 C s0 s 15 - s8 page program 02h a23 C a16 a15 C a8 a7 C a0 d7 C d0 quad page program 3 2h a23 C a16 a15 C a8 a7 C a0 d7 C d0 , (3) sector erase (4kb) 20h a23 C a16 a15 C a8 a7 C a0 block er ase (32kb) 52h a23 C a16 a15 C a8 a7 C a0 block erase (64kb) d8h a23 C a16 a15 C a8 a7 C a0 chip erase c7h /60h erase / program suspend 75h erase / program resume 7ah power - down b9h continuous read mode reset (4) ffh ffh notes: 1. data bytes are shifted wi th most significant bit first. byte fields with data in parenthesis () indicate data being read from the device on the do pin. 2. the status register contents will repeat continuously until /cs terminates the instruction. 3. quad page program input data : io0 = d4, d0, io1 = d5, d1, io2 = d6, d2, io3 = d7, d3, 4. this instruction is recommended w hen using the dual or quad continuous read mode feature. see section 7 .2. 1 9 & 7 .2. 20 for more information.
w25q128bv - 20 - 7.2.3 instr uction set table 2 ( read instructions) instruction name byte 1 ( code ) byte 2 byte 3 byte 4 byte 5 byte 6 read data 03h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) fast read 0bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) fast read dual output 3bh a23 - a16 a15 - a8 a7 - a0 dummy ( d7 - d0 , ) (1) fast read quad output 6bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (3) fast read dual i/o bbh a23 - a 8 (2) a7 - a0, m7 - m0 (2) (d7 - d0 , ) (1) fast read quad i/o ebh a23 - a0, m7 - m0 (4) ( x,x,x,x, d7 - d0 , ) (5) (d7 - d0, ) (3) word read quad i/o (7) e7h a23 - a0, m7 - m0 (4) ( x,x, d7 - d0 , ) (6) (d7 - d0, ) (3) octal word read quad i/o (8) e3h a23 - a0, m7 - m0 (4) (d7 - d0, ) (3) set burst with wrap 77h xxxxxx , w 6 - w 4 (4) notes : 1 . dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2 . dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 3 . quad output data io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3, ..) 4 . qua d input address set burst with wrap input io0 = a20, a16, a12, a8, a4, a0, m4, m0 io0 = x, x, x, x, x, x, w4, x io1 = a21, a17, a13, a9, a5, a1, m5, m1 io1 = x, x, x, x, x, x, w5, x io2 = a22, a18, a14, a10, a6, a2, m6, m2 io2 = x, x, x, x, x, x, w6, x io3 = a23, a19, a15, a11, a7, a3, m7, m3 io3 = x, x, x, x, x, x, x, x 5 . fast read quad i/o data io0 = (x, x, x, x, d4, d0, ..) io1 = (x, x, x, x, d5, d1, ..) io2 = (x, x, x, x, d6, d2, ..) io3 = (x, x, x, x, d7, d3, ..) 6. word read quad i/o data io0 = (x, x, d4, d0, ..) io1 = (x, x, d5, d1, ..) io2 = (x, x, d6, d2, ..) io3 = (x, x, d7, d3, ..) 7 . the lowest address bit must be 0. ( a0 = 0 ) 8. the lowest 4 address bits must be 0. ( a0, a1, a2, a3 = 0 )
w25q128bv publication release date: october 03 , 201 3 - 21 - revision h 7.2.4 instruction set table 3 (id, security instructions) instruction name byte 1 ( code ) byte 2 byte 3 byte 4 byte 5 byte 6 release power down / device id abh dummy dummy dummy (id7 - id0) (1) manufacturer/ device id ( 2 ) 90h dummy dummy 00h (mf7 - mf0 ) (id7 - id0) manufacturer/device id by dual i/o 92h a23 - a8 a7 - a0, m[7:0] (mf[7:0], id[7:0]) manufacture/device id by quad i/o 94h a23 - a0, m[7:0] xxxx, (mf[7:0], id[7:0]) (mf[7:0], id[7:0], ) jedec id 9fh (mf7 - mf0) manufacturer (id15 - id8) memory type (id7 - id0) capacity read unique id 4bh dummy dummy dummy dummy (id63 - id0) read sfdp register 5ah 00h 00h a7 C a0 dummy (d7 - 0) erase security registers (3) 44h a23 C a16 a15 C a8 a7 C a0 program security registers (3) 42h a23 C a16 a15 C a8 a7 C a0 d7 - d0 d7 - d0 rea d security registers (3) 48h a23 C a16 a15 C a8 a7 C a0 dummy (d7 - 0) notes: 1. the device id will repeat continuously until /cs terminates the instruction. 2. see manufacturer and device identification table for device id information. 3. security register address: sec urity register 1 : a23 - 16 = 00h ; a15 - 8 = 10h ; a7 - 0 = byte address security register 2 : a23 - 16 = 00h ; a15 - 8 = 20h ; a7 - 0 = byte address security register 3 : a23 - 16 = 00h ; a15 - 8 = 30h ; a7 - 0 = byte address
w25q128bv - 22 - 7.2.5 write enable (06 h) the write en able instruc tion (figure 4 ) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, quad page program, sector erase, block erase , chip erase, write status register and erase/program security registers i nstruction. the write enable instruction is entered by driving /cs low, shifting the instruction code 06h into the data input (di) pin on the rising edge of clk, and then driving /cs high. figure 4. write en able instruction s equence diagram 7.2.6 write enable for volatile status register (50h) t he non - volatile status register b it s described in section 7 .1 can also be written to as volatile bits. this gives more flexibility to change the system configuration and memory protection sch eme s quickly without waiting for the typical non - volatile bit write cycles or affecting the endurance of the status register non - volatile bits. to write the volatile values into the status register bits, the write enable for volatile status register (50h) instruction must be issued prior to a write status register (01h) instruction. write enable for volatile status register instruction (figure 5) will not set the write enable latch (wel) bit, it is only valid for the write status register instruction to cha nge the volatile status register bit value s . figure 5. write enable for volatile status register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (06h) high impedance /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (50h) high impedance
w25q128bv publication release date: october 03 , 201 3 - 23 - revision h 7.2.7 write disable (04 h) the write dis able instruction (figure 6 ) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving /cs low, shifting the instructio n code 04h into the di pin and then driving /cs high. note that the wel bit is automatically reset after power - up and upon completion of t he write status register, erase/program security registers, page program, quad page program, sector erase, block erase and chip erase instructions. write disable instruction can also be used to invalidate the write enable for volatile status register instr uction. figure 6 . write dis able instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (04h) high impedance
w25q128bv - 24 - 7.2.8 read status register - 1 (05h) and read status register - 2 ( 3 5h) the read status register instruction s allow the 8 - bit status register s to be read. the instruction is e ntered by driving /cs low and shifting the instruction code 05h for status r egister - 1 or 35h for status r egister - 2 into the di pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with mo st significant bit (msb) first as shown in figure 7 . the status register bits are shown in figure 3 a and 3b and include the busy, wel, bp 2 - bp 0 , tb , sec, srp0, srp1 , qe , lb[3:1] , cmp and sus bits (see status register section earlier in this datasheet ). the read status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. the status register can be read continuously, as shown in figure 7 . the instruction is completed by driving /cs high. figure 7 . read status register instruction sequence diagram 7.2.9 write status register (01h) the write status register instruc tion allows the status register to be written. only non - volatile status register bits srp0, sec, tb, bp2, bp1, bp0 (bits 7 thru 2 of status registe r - 1) and cmp, lb3, lb2, lb1 , qe, srp1 (bits 14 thru 8 of status register - 2) can be written to. all other stat us register bit locations are read - only and will not be affected by the write s tatus register instruction. lb[3:1] are non - volatile otp bits, once it is set to 1, it can not be cleared to 0. the status register bits are shown in figure 3 and described in 7 .1 . to write non - volatile status register bits, a standard write enable (06h) instruction must previously have been executed for the device to accept the write status register instruction (status register bit wel must equal 1). once write enabled, the inst ruction is entered by driving /cs low, sending the instruction code 01h, and then writing the status register data b yte as illustrated in figure 8 . to write volatile status register bits, a write enable for volatile status register (50h) instruction must have been executed prior to the wr ite status register instruction (status register bit wel remains 0). howe ver, srp1 and lb3, lb2, lb1 can not be changed from 1 to 0 because of the otp protection for these bits. upon power off, the volatile status reg ister bit values will be lost, and the non - volatile status register bit values will be restored when power on again. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (05h or 35h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 status register 1 or 2 out status register 1 or 2 out * * = msb *
w25q128bv publication release date: october 03 , 201 3 - 25 - revision h to complete the write status register instruction, t he /cs pin must be driven high after the eighth or sixteenth bit of data that is clock ed in. if this is not done the write status register instruction will not be executed. if /cs is driven high after the eighth clock (compatible with the 25x series) the cmp and qe bits will be cleared to 0. during non - volatile status register write operati on (06h combined with 01h), a fter /cs is driven high, the self - timed write status register cycle will commence for a time duration of t w (see ac characteristics). while the write status register cycle is in progress, the read status register instruction ma y still be accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept other instructions again. after the write status register cycle has finished , the wri te enable latch (wel) bit in the status register will be cleared to 0. during volatile status register write operation (50h combined with 01h), after /cs is driven high, the status register bits will be refreshed to the new values within the time period of t shs l2 (see ac characteristics). busy bit will remain 0 during the status register bit refresh period. please refer to 7 .1 for detailed status register bit descriptions . factory default for all status register bits are 0. figu re 8 . write status register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (01h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 status register 1 in status register 2 in mode 0 mode 3 * * = msb *
w25q128bv - 26 - 7.2.10 read data (03h) the read data instruction allows one or more data bytes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruc tion code 03h followed by a 24 - b it address (a23 - a0) into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving /cs high. the read data instruction sequence is shown in figure 9 . if a read data instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 9 . read data instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (03h) high impedance 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 7 6 5 4 3 2 1 0 7 24-bit address 23 22 21 3 2 1 0 data out 1 * * = msb *
w25q128bv publication release date: october 03 , 201 3 - 27 - revision h 7.2.11 fast read (0bh) the fast read instruction is similar to the read data instruction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight d ummy clocks after the 24 - bit address as shown in figure 10 . the dummy clocks allow the devices internal circuits additional time for setting up the initial address. during the dummy clocks the data value on the d o pin is a dont care. figure 10 . fas t read instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (0bh) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy clocks high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 43 31 0 = msb *
w25q128bv - 28 - 7.2.12 fast read dual output (3bh) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruction except th at data is output on two pins ; i o 0 and io 1 . this allows data to be transferred fro m the w25q128b v at twice the rate of standard spi devices. the fast read dual output instruction is ideal for quickly downloading code from flash to ram upon power - up or for applications that cache code - segments to ram for execution. similar to the fast r ead instruction, the fast read dual output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 1 1 . the dummy cl ocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is dont care. however, the io 0 pin should be high - impedance prior to the falling edge of the first data out clock. figure 1 1 . fast read dual output instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (3bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 6 4 2 0 24-bit address 23 22 21 3 2 1 0 * * 31 31 /cs clk di (io 0 ) do (io 1 ) dummy clocks 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 7 5 3 1 high impedance 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 io 0 switches from input to output 6 7 data out 1 * data out 2 * data out 3 * data out 4 = msb *
w25q128bv publication release date: october 03 , 201 3 - 29 - revision h 7.2.13 fast read quad output (6bh) the fast read quad output (6bh) instruction is similar to the fast read dual output (3bh) instruction except that data is output on four pi ns, io 0 , io 1 , io 2 , and io 3 . a quad enable of status register - 2 must be executed before the device will accept the fast read quad output instruction (status register bit qe must equal 1 ) . the fast read quad output instruction allows data to be transferred f rom the w25q128b v at four times the rate of stan dard spi devices. t he fast read q ua d output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 1 2 . the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is dont care. however, the io pins should be high - impedance prior to t he falling edge of the first data out clock. figure 1 2 . fast read quad output instruction sequence diagram /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (6bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk dummy clocks 0 40 41 42 43 44 45 46 47 5 1 high impedance 4 5 byte 1 high impedance high impedance 6 2 7 3 high impedance 6 7 high impedance 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 4 io 0 switches from input to output io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 = msb *
w25q128bv - 30 - 7.2.14 f ast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23 - 0) two bits per clock. this reduced instruction overhead may allow for code execution (xip) directly from the d ua l spi in some applicatio ns. fast read dual i/o with continuous read mode the fast read dual i/o instruction can further reduce instruction overhead through setting the co ntinuous read mode b its (m7 - 0) after the input address bits (a23 - 0), as shown in figure 1 3 a . the upper nib ble of the (m7 - 4) controls the length of the next fast read dual i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bit s m 5 - 4 = (1, 0 ) , then the next fast read dual i/o instruction ( after /cs is raised and then lowered) does not require the bbh instruction code, as shown in figure 1 3 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bit s m 5 - 4 do not equal to ( 1 ,0) , the next instruction ( after /cs is raised and then lowered ) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before issuing normal instructions (see 7 .2. 20 for detail descriptions). figure 1 3 a . fast read du al i / o instruction sequence ( initial instruction or previous m 5 - 4 ? 1 0 ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (bbh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 23 /cs clk di (io 0 ) do (io 1 ) 0 32 33 34 35 36 37 38 39 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 22 19 23 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 = msb * *
w25q128bv publication release date: october 03 , 201 3 - 31 - revision h figure 1 3 b . fast read dual i / o instruction sequence ( previous instruction set m 5 - 4 = 1 0 ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 15 /cs clk di (io 0 ) do (io 1 ) 0 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 22 19 23 * = msb *
w25q128bv - 32 - 7.2.15 fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh) instruction except that address and data bits are input and output through four pins io 0 , io 1 , io 2 and io 3 and four dummy clock are required prior to the data output . the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad e nable bit (qe) of status register - 2 must be set to enable the fast r ead quad i/o instruction . fast read quad i/o with continuous read mode the fast read quad i/o instruct ion can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in figure 1 4 a . the upper nibble of the (m7 - 4) controls the length of the next fast read quad i/o instruction t hrough the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mo de bit s m 5 - 4 = (1, 0 ) , then the next fast read quad i/o instruction ( after /cs is raised and then lowered) does not require the ebh instruction code, as shown in figure 1 4 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bit s m 5 - 4 do not equal to ( 1 ,0) , the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before issuing normal instructions (see 7 .2. 20 for detail descriptions). figure 1 4 a . fast read quad i / o instruction sequence ( i nitial instruction or previous m 5 - 4 ? 1 0 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 22 23 dummy dummy instruction (ebh)
w25q128bv publication release date: october 03 , 201 3 - 33 - revision h figure 1 4 b . fast read quad i / o instruction sequence ( previous instruction set m 5 - 4 = 1 0 ) fast read quad i/o with 8/16/32/64 - byte wrap around the fast read quad i/o instruction can also be used to access a specific portion within a page by issui ng a set burst with wrap command prior to ebh . the set burst with wrap command can either enable or disable the wrap around feature for the following ebh c ommands . when wrap around is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read commands. the set burst with wrap instruction allows three wrap bits, w6 - 4 to be set . the w4 bit is used to enable or disable the wrap around op eration while w6 - 5 are used to specify the length of the wrap around section within a page. see 7 .2.1 8 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 dummy dummy
w25q128bv - 34 - 7.2.16 word read quad i/o (e7h) the word read quad i/o (e 7 h) instruction is similar to the fast read quad i/o ( e bh) instruction excep t that the lowest a ddress bit (a0) must equal 0 and only two dummy clocks are required prior to the data output . the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the q uad e nable bit (qe) of status register - 2 must be set to enable the word r ead quad i/o instruction . word read quad i/o with continuous read mode the word read quad i/o instruction can further reduce instruction overhead through setting the continuous rea d mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in figure 1 5 a . the upper nibble of the (m7 - 4) controls the length of the next fast read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction ( after /cs is raised and then lowered) does not require the e7h instruction code, as shown in figure 1 5b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mo de bits m5 - 4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) befor e iss uing normal instructions (see 7 .2. 20 for detail descriptions). figure 1 5 a . word read quad i / o instruction sequence ( initial instruction or previous m 5 - 4 ? 10 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 dummy instruction (e7h)
w25q128bv publication release date: october 03 , 201 3 - 35 - revision h figure 1 5 b . word read quad i / o instruction sequence ( previous instruction set m 5 - 4 = 1 0 ) word read quad i/o with 8/16/32/64 - byte wrap around the word read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap command prior to e7h. the set burst with wrap command can either enable or disable the wrap around feature for the following e7h commands. when wrap around is enabled, the data being accessed can be limited t o either an 8, 16, 32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning bounda ry automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data witho ut issuing multiple read commands. the set burst with wrap instruction allows three wrap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6 - 5 are used to specify the length of the wrap arou nd section wit hin a page. see 7 .2.18 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 dummy
w25q128bv - 36 - 7.2.17 octal word read quad i/o (e3h) the octal word read quad i/o (e3h) instruction is similar to the fast read quad i/o (ebh) instruction except that the lower four address bits (a0, a1 , a2, a3 ) must equal 0. as a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (xip). the quad enable bit (qe) of status register - 2 must be se t to enable the octal word r ead quad i/o instr uction. octal word read quad i/o with continuous read mode the octal word read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in figure 1 6 a. the upper nibble of the (m7 - 4) controls the length of the next octal word read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins sh ould be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction ( after /cs is raised and then lowered) does not require the e3h instruction code, as shown in figure 1 6b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction ( after /cs is r aised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before iss uing normal instructions (see 7 .2. 20 for detail descriptions). f igure 1 6 a. octal word read quad i/o instruction sequence ( initial instruction or previous m 5 - 4 ? 10 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 instruction (e3h) 4 0 5 1 6 2 7 3 byte 4
w25q128bv publication release date: october 03 , 201 3 - 37 - revision h figure 1 6 b. octal word read quad i/o instruction sequence ( previous instruction set m 5 - 4 = 1 0 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 byte 4
w25q128bv - 38 - 7.2.18 set burst with wrap (77h) the set burst with wra p (77h) instruction is used in conjun ction with fast read quad i/o and word read quad i/o instructions to access a fixed length of 8/16/32/64 - byte section within a 256 - byte page. certain applications can benefit from this feature and improve the overal l system code execution performance. similar to a quad i/o instruction, the set burst with wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code 77h followed by 24 dummy bit s and 8 wrap bits , w7 - 0 . the instruct ion sequence is shown in figure 17. wrap bit w7 and the lower nibble w3 - 0 are not used. w6, w5 w4 = 0 w4 =1 (default) wrap around wrap length wrap around wrap length 0 0 yes 8 - byte no n/a 0 1 yes 16 - byte no n/a 1 0 yes 32 - byte no n/a 1 1 yes 64 - b yte no n/a once w6 - 4 is set by a set burst with wrap instruction, all the following fast read quad i/o and word read quad i/o instructions will use the w6 - 4 setting to access the 8/16/32/64 - byte section within any page. to exit the wrap around func tion and return to normal read operation, another set burst with wrap instruction should be issued to set w4 = 1. the default value of w4 upon power on is 1. in the case of a system reset while w4 = 0, it is recommended that the controller issues a set bur st with wrap instruction to reset w4 = 1 prior to any normal read instructions since w25q128b v does not have a hardware reset pin . figure 17. set burst with wrap instruction sequence wrap bit /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 x x x x x x x x don't care 6 7 8 9 don't care don't care 10 11 12 13 14 15 instruction (77h) mode 0 mode 3 x x x x x x x x x x x x x x x x w4 x w5 x w6 x x x
w25q128bv publication release date: october 03 , 201 3 - 39 - revision h 7.2.19 continuous read mode bits (m7 - 0) the continuous read mode bits are used in conjunction with fast read dual i/o, fast read quad i/o, word read quad i/o and octal word read quad i/o instructions to provide the highest random flash memory access rate with minimum spi instruction overhead, thus allow true xip (execute in place) to be performed on serial flash devices. m7 - 0 need to be set by the dual/quad i/o read instructions. m 5 - 4 are used to control whether the 8 - bit spi instruction code (bbh, ebh, e7h or e3h) is needed or not for the next command. when m 5 - 4 = (1, 0 ) , the next command will be treated same as the current dual/quad i/o read command without needing the 8 - bit instruction code; when m 5 - 4 do not equal to (1,0) , the device returns to normal spi mode, all commands can be accepted. m7 - 6 and m3 - 0 are reserved bi ts for future use, either 0 or 1 values can be used. 7.2.20 continuous read mode reset (ffh or ffffh) continuous read mode reset instruction can be used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi operation , as sh own in figure 18. figure 1 8 . continuous read mode reset for fast read dual/quad i/o since w25q128b v does not have a hardware reset pin, so if the controller resets while w25q128b v is set to continuous mode read, the w25q128b v will not recognize any initial standard spi instructions from the controller . to address this possibility, it is recommended to issue a continuous read mode reset instruction as the first instruction after a system reset. doing so will release the device f rom the continuous read mode and allow standard spi instructions to be recognized. to reset continuous read mode during quad i/o operation, only eight clocks are needed. the instruction is ffh. to reset continuous read mode during dual i/o operation, sixteen clocks are needed to shift in instruction ffffh. /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 don't care 6 7 8 9 10 11 12 13 14 15 mode bit reset for quad i/o (ffh) mode 0 mode 3 mode bit reset for dual i/o (ffffh) don't care don't care
w25q128bv - 40 - 7.2.21 pa ge program (02h) the page program instruction allows from one byte to 256 bytes ( a page) of data to be programmed at previously erased (ffh) memory locations. a write enable instruction must b e executed before the device will accept the page program instruction (status register bit wel = 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 02h followed by a 24 - bit address (a23 - a0) and at l east one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 1 9 . if an entire 256 byte page is to be programmed, the last addr ess byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes ( a partial page) can be programmed without having any effect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. if more than 256 bytes are sent to the d evice the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page p rogram instruction will not be executed. after /cs is driven high, the self - timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the page program cycle has finishe d the write enable latch (wel) bit in the status register is cleared to 0. the page program instruction will not be executed if the addressed page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits . figu re 1 9 . page program instruction sequence diagram /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (02h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q128bv publication release date: october 03 , 201 3 - 41 - revision h 7.2.22 quad input page program ( 3 2h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io 0 , io 1 , io 2 , and io 3 . the qua d page program can improve performance for prom programmer and applications that have slow clock speeds <5mhz. systems with faster clock speed will not realize much benefit for the quad page program instruction since the inherent page program time is much greater than the time it take to clock - in the data. to use quad page program the quad enable in status register - 2 must be set (qe=1). a write enable instruction must be executed before the device will accept the quad page program instruction (status regist er - 1, wel=1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 32h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the io pins. the /cs pin must be held low for the entire length of the ins truction while data is being sent to the device. all other functions of quad page program are identical to standard page program. the quad page program instruction sequence is shown in figure 20 . figure 20 . quad input page program instruction sequence diagram /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (32h) 8 9 10 28 29 30 32 33 34 35 36 37 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk 5 1 byte 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 256 0 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 536 537 538 539 540 541 542 543 mode 0 mode 3 byte 253 byte 254 byte 255 io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 * * * * * * * = msb *
w25q128bv - 42 - 7.2.23 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the sector erase instruction (sta tus register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 20h followed a 24 - bit sector address (a23 - a0) (see figure 2). the sector erase instructi on sequence is shown in figure 2 1 . the / cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after /cs is driven high, the self - timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be executed if the addressed p age is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits (see status register memory protection table). figure 2 1 . sector erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (20h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q128bv publication release date: october 03 , 201 3 - 43 - revision h 7.2.24 32kb block erase (52h) the block erase instruction sets all memory within a specified block ( 32 k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /c s pin low and shifting the instruction code 52 h followed a 24 - bit block address (a23 - a0) (see figure 2). the block erase instructio n sequence is shown in figure 2 2 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. i f this is not done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commence for a time duration of t be 1 (see ac characteristics). while the block erase cycle is in progress, the read s tatus register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the bloc k erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 2 2 . 32kb block erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (52h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q128bv - 44 - 7.2.25 64kb block erase (d8h) the block erase instruction sets all memory within a specified block (64k - bytes) to the erased state of all 1s (ffh). a write enable i nstruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code d8h followed a 24 - bit block address (a 23 - a0) (see figure 2). the block erase instructio n sequence is shown in figure 2 3 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is dr iven high, the self - timed block erase instruction will commence for a time duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits (see status register memory protection table). figure 2 3 . 64kb block erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (d8h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q128bv publication release date: october 03 , 201 3 - 45 - revision h 7.2.26 chip erase (c7h / 60h ) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instru ction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code c7h or 60h . the chip erase instructio n sequence is shown in figure 2 4 . the /cs pin must be driven high after the eig hth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self - timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. after the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits (see status registe r memory protection table). figure 2 4 . chip erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (c7h/60h) high impedance mode 0 mode 3
w25q128bv - 46 - 7.2.27 erase / program s uspend (75h) the erase /program suspend instruction 75h , allows the system to interrupt a s ector or b lock e rase operation or a pa ge program operation and then read from or p rogram /erase data to , any other sector s or block s . the erase/program suspend instruction sequence is shown in figure 25. the write status register instruction (01h) and erase instructions (20h, 52h, d8 h , c7h, 60h , 44h ) are not allowed during erase s uspend. erase suspend is valid only during the s ector or b lock erase operation . if written during the c hip e rase operatio n , the erase suspend instruction is ignored. the write status register instruction (01h) and progr am instructions (02h, 32h, 42h) are not allowed during program suspend. program suspend is valid only during the page program or quad page program operation. the erase/program suspend instruction 75h will be accepted by the device only if the sus bit in the status register equals to 0 and the busy bit equals to 1 while a sector or block erase or a page program operation is on - going. if the sus bit equals to 1 or the busy bit equal s to 0, the suspend instruction will be ignored by the device. a maximum of time of t sus (see ac characteristics) is required to suspend the erase or program operation. the busy bit in the status r egister will be clear ed from 1 to 0 within t sus and the sus bit in the status register will be set from 0 to 1 immediately after er ase /program suspend. for a previously resumed erase/program operation, it is also required that the suspend instruction 75h is not issued earlier than a minimum of time of t sus following the preceding resume instruction 7ah. unexpected power off duri ng the erase/program suspend state will reset the device and release the suspend state. sus bit in the status register will also reset to 0. the data within the page, sector or block that was being suspended may become corrupted. when the device is powered up again, i t is recommended for the user to repeat the same erase or program operation that was interrupted, at the same address location, to avoid the potention data corruption. figure 2 5 . erase /program suspend instruction s equence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (75h) high impedance mode 0 mode 3 tsus accept instructions
w25q128bv publication release date: october 03 , 201 3 - 47 - revision h 7.2.28 erase / program resume (7ah) the erase /program resume instruction 7ah must be written to resume the s ector or b lock e rase operation or the page program operation after an erase /program suspend . the resume instruction 7ah will be accepted by t he device only if the sus bit in the status register equals to 1 and the busy bit equals to 0. after iss ued the sus bit will be clear ed from 1 to 0 immediately , the busy bit will be set from 0 to 1 within 200ns and the s ector or b lock will complete the era se operation or the page will complete the program operation . if the sus bit equals to 0 or the busy bit equals to 1, the resume instruction 7a h will be ignored by the device. the erase/program resume instruction sequence is shown in figure 26. resume in struction is ignored if the previous erase/program suspend operation was interrupted by unexpected power off. it is also required that a subsequent erase/program suspend instruction not to be issued within a minimum of time of t sus following a previous r esume instruction. figure 2 6 . erase /program resume instruction sequence /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (7ah) mode 0 mode 3 resume previously suspended program or erase
w25q128bv - 48 - 7.2.29 power - down (b9h) although the standby current during normal operation is relatively low, standby current can be further reduced with the power - down instr uction. the lower power consumption makes the power - down instruction especially useful for battery powered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code b9 h as shown in figure 2 7 . the /cs pin must be driven high after the eighth bit has been latched. if this is not done the power - down instruction will not be executed. after /cs is driven high, the power - down state will entered within the time duration of t dp (see ac characteristics). while in the power - down state only the release from power - down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status regist er instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. the device always powers - up in the normal operation with the standby cu rrent of icc1. figure 2 7 . deep power - down instruction sequence diagram /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (b9h) mode 0 mode 3 tdp power-down current stand-by current
w25q128bv publication release date: october 03 , 201 3 - 49 - revision h 7.2.30 release power - down / device id (abh) the release from power - down / device id instruction is a multi - purpose instruction. it can be used to release the d evice from the power - down state , or obtain the devices electronic ident ification (id) number . to release the device from the power - down state, the instruction is issued by driving the /cs pin low, shifting the instruction code abh and driving /cs high as shown in figure 2 8 a . release from power - down will take the time duration of t res 1 (see ac characteristics) before the device will resume normal operation and other instructions are accepted. the /cs pin must remain high during the t res 1 time duration. when used only to obtain the device id while not in the power - down state, the instruction is initiated by driving the /cs pin low and shifting the instruction code abh followed by 3 - dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 2 8 a . the d evice id values for the w25q128b v is listed in manufacturer and device identification table. the device id can be read continuously. the instruction is completed by driving /cs high . when used to release the device from the power - down state and obtain the device id, the instruction is the same as previously described, and shown in figure 2 8 b , except that after /cs is driven high it must remain high for a time duration of t res 2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from power - down / device id instruction is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle . figure 2 8 a . release power - down instruction sequence /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) mode 0 mode 3 tres1 power-down current stand-by current
w25q128bv - 50 - figure 2 8 b . release power - down / device id instruction sequence diagram tres2 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) high impedance 8 9 29 30 31 3 dummy bytes 23 22 2 1 0 * mode 0 mode 3 7 6 5 4 3 2 1 0 * 32 33 34 35 36 37 38 device id power-down current stand-by current = msb *
w25q128bv publication release date: october 03 , 201 3 - 51 - revision h 7.2.31 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power - down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power - down / device id instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 90h followed by a 24 - bit address (a23 - a0) of 000 000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of clk with most significant bit ( msb) first as shown in figure 29 . the device id values fo r the w25q128b v is listed in manufacturer and device i dentification table. if the 24 - bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction i s completed by driving /cs high. figure 29 . read manufacturer / device id diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (90h) high impedance 8 9 10 28 29 30 31 address (000000h) 23 22 21 3 2 1 0 device id * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 manufacturer id (efh) 40 41 42 44 45 46 7 6 5 4 3 2 1 0 * 43 31 0 mode 0 mode 3 = msb *
w25q128bv - 52 - 7.2.32 read manufacturer / device id dual i/o (92h) the manufacturer / device id dual i/o instruction is an alternative to the read manufacturer/devic e id instruction that provides both the jedec assigned manufacturer id and the specific device id at 2x speed. the read manufactur er / device id dual i/o instruction is similar to the fast read dual i/o instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 9 2 h followed by a 24 - bit address (a23 - a0) of 000000h , 8 - bit continuous read mode bits, with the capability to input the address bits two bits per clock . after which, the manufacturer id for winbond (efh) and the device id are shifted out 2 bits per clock on the falling edge of clk with most significant bit s (msb) first as shown in figure 3 0 . the device id values for the w25q128b v is listed in manufacturer and device identification table. if the 24 - bit addr ess is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. fig ure 3 0 . read manufacturer / device id dual i/o diagram note: the c ontinuous read mode bits m 7 - 0 must be set to fxh to be compatible with fast read dual i/o instruction. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (92h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 5 3 1 * * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 23 * * a23-16 a15-8 a7-0 (00h) m7-0 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 0 mode 0 mode 3 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 6 4 2 1 0 1 mfr id device id mfr id (repeat) device id (repeat) ios switch from input to output * * * * = msb *
w25q128bv publication release date: october 03 , 201 3 - 53 - revision h 7.2.33 read manufacturer / device id quad i/o (94h) the read manufacturer / device id quad i/o instruction is an alternative to the read manufacturer / device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 4x speed . the read manufacturer / device id quad i/o instruction is similar to the fast read quad i/o instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 9 4 h followed by a 24 - bit address (a23 - a0) of 000000h , 8 - bit continuous read mode bits and then four clock dummy cycles, with the capabil ity to input the address bits four bits per clock . after which, the manufacturer id for winbond (efh) and the device id are shifted out four bits per clock on the falling edge of clk with most significant bit (msb) first as shown in figure 3 1 . the device i d values for the w25q128b v is listed in manufacturer and device identification table. if the 24 - bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read c ontinuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 3 1 . read manufacturer / device id quad i/o diagram note: the c ontinuous read mode bits m7 - 0 must be set to fxh to be compatible with fast read qu ad i/o instruction. mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (94h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 5 1 4 0 23 mode 0 mode 3 ios switch from input to output high impedance 7 3 6 2 /cs clk io 0 io 1 io 2 io 3 high impedance a23-16 a15-8 a7-0 (00h) m7-0 mfr id device id dummy dummy /cs clk io 0 io 1 io 2 io 3 23 0 1 2 3 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 24 25 26 27 28 29 30 mfr id (repeat) device id (repeat) mfr id (repeat) device id (repeat)
w25q128bv - 54 - 7.2.34 read unique id number (4bh) the read unique id number instruction accesses a factory - set read - only 64 - bit number that is unique to each w25q128b v device. the id number can be used in conjunction with user software methods to help preve nt copying or cloning of a system. the read unique id instruction is initiated by driving the /cs pin low and shifting the instruction code 4bh followed by a four bytes of dummy clocks. after which, the 64 - bit id is shifted out on the falling edge of clk as shown in figure 3 2 . figure 3 2 . read unique id number instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (4bh) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 mode 0 mode 3 * dummy byte 1 dummy byte 2 39 40 41 42 dummy byte 3 dummy byte 4 63 62 61 2 1 0 64-bit unique serial number 100 101 102 high impedance = msb *
w25q128bv publication release date: october 03 , 201 3 - 55 - revision h 7.2.35 read jedec id (9fh) for compatibility reasons, the w25q128b v provides several instructions to electronically determine the identity of the device. the read jedec id instru ction is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruction code 9fh. the jedec assigned manufacturer id byte for winbond (e fh) and two device id bytes, memory type (id15 - id8) and capacity (id7 - id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 3 3 . for memory type and capacity values refer to manufacturer and device ide ntification table. figure 3 3 . read jedec id instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (9fh) high impedance 8 9 10 12 13 14 15 capacity id7-0 /cs clk di (io 0 ) do (io 1 ) 16 17 18 19 20 21 22 23 manufacturer id (efh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 * 27 15 mode 0 mode 3 11 7 6 5 4 3 2 1 0 * memory type id15-8 = msb *
w25q128bv - 56 - 7.2.36 read sfdp register (5ah) the w25q1 28b v features a 256 - byte serial flash discoverable parameter (sfdp) register that co ntains information about device configurati ons, available instructions and other features . the sfdp parameters are stored in one or more parameter identification (pid) tables. currently only one pid table is specified , but more may be added in the future. the read sfdp register instruction is com pa tible with the sfdp standard initially established in 2010 for pc and other applications , as well as the jedec standard jesd216 that is published in 2011 . most winbond spif lash memories shipped after june 2011 (date code 112 4 and beyond) support the sfdp f eature as specified in the app licable data sheet. the read sfdp instruction is initiated by driving the /cs pin low and shifting the instruction code 5ah followed by a 24 - bit address (a23 - a0) (1) into the di pin. eight dummy clocks are also required bef ore the sfdp register contents are shifted out on the falling edge of the 40 th clk with most significant bit (msb) first as shown in figure 3 4 . for sfdp register values and descriptions, please refer to the winbond application note for sfdp definition t abl e. note 1: a23 - a8 = 0; a7 - a0 are used to define the starting byte address for the 256 - byte sfdp register. figure 3 4 . read sfdp register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (5ah) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q128bv publication release date: october 03 , 201 3 - 57 - revision h 7.2.37 erase security registers (44h) the w25q128b v offers three 256 - byte security registers which can be erased and programmed individually. these registers may be used by the system manufacturers to store security and other important information separately from the main memory array. the erase security register instruction is similar to the sect or erase instruction . a write enable instruction must be executed before th e device will accept the erase security register instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruc tion code 44 h followed by a 24 - bit address (a23 - a0) to erase one of the three security register s . address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 dont care security register #2 00h 0 0 1 0 0 0 0 0 dont care security regist er #3 00h 0 0 1 1 0 0 0 0 dont care the erase security register instruction sequence is shown in figure 3 5 . the /cs pin must be driven high after the eighth bit of the last byte has been l atched. if this is not done the instruction will not be executed . after /cs is dri ven high, the self - timed erase security register operation will commence for a time duration of t se (see ac characteristics). while the erase security register cycle is in progress, the read status register instruction may still be access ed for checking the status of the busy bit. the busy bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the erase security register cycle has finished the write ena ble latch (wel) bit in the status register is cleared to 0. t he security register lock bits lb [3:1] in the status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permane ntly locked, erase security register instruction to that register will be ignored (see 7 .1.9 for detail descriptions). figure 3 5 . erase security registers instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (44h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q128bv - 58 - 7.2.38 program security registers (42h) the program security register instruction i s similar to the page program instruction. it allows from one byte to 256 bytes of security register data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the program se curity register instruction (status register bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 42h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the di pin. the /cs pin must b e held low for the entire length of the instruction while data is being sent to the device. address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register # 3 00h 0 0 1 1 0 0 0 0 byte address the program security register instruction sequence is shown in figure 3 6 . the se curity register lock bits lb[3:1] in the status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, program security register instruction to that register will be ignored (see 7 .1.9 , 7 .2. 2 1 for detail descriptions). figure 3 6 . program security registers instruction sequence /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (42h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q128bv publication release date: october 03 , 201 3 - 59 - revision h 7.2.39 read securit y registers (48h) the read security register instruction is similar to the fast read instruction and allows one or more data bytes to be sequentially read from o ne of the three security registers. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 48h followed by a 24 - bit address (a23 - a0) and eight dummy clocks into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addresse d memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the byte address is automatically incremented to the next byte address after each byte of data is shifted out . o nce the byte address reach es the last byte of the register (byte ffh), it will reset to 00h, the first byte of the register, and continue to increment. the instruction is completed by driving /cs high. the read security register instruction sequence is shown in figure 3 7 . if a read security register instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read security register instruction allows clock rates from d.c. to a m aximum of f r (see ac electrical characteristics). address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address f igure 3 7 . read security registers instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (48h) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q128bv - 60 - 8. electrical character istics 8.1 absolute maximum ratings (1) (2) parameters symbol conditions range unit supply voltage vcc C 0.6 to vcc+0. 6 v voltage applied to any pin v io relative to ground C 0.6 to vcc +0.4 v transient voltage on any pin v iot <20ns transient relative to ground C 2 .0v to vcc+ 2 .0v v storage temperature t stg C 65 to +150 c lead temperature t lead see note c electrostatic discharge voltage v esd (3) human body model C 2000 to +2000 v not es: 1.this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is no t guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum ratings may cause permanent damage. 2. jedec std jesd22 - a114a (c1=100pf, r1=1500 ohms, r2=500 ohms). 3.compliant with jedec standard j - std - 20c for small body sn - pb or pb - free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 20 02/95/eu. 8.2 operating ranges parameter symbol conditions spec unit min max supply voltage vcc (1) f r = 7 0 mhz ( dual i/o & quad spi) f r = 104 mhz (single / dual output) fr = 33mhz 2.7v 3.6v v ambient temperature, operating t a industrial - 40 +85 c note: 1. vcc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage.
w25q128bv publication release date: october 03 , 201 3 - 61 - revision h 8.3 power - up timing and write inhibit threshold ( 1 ) parameter symbol spec unit min max vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1 .0 2.0 v note: 1. these parameters are characterized only. figure 3 8 . power - up timing and voltage levels figure 43b. power - up, power - down requirement vcc tvsl read instructions allowed device is fully accessible tpuw /cs must track vcc program, erase and write instructions are ignored reset state vcc (max) vcc (min) v wi time vcc time / cs must track vcc during vcc ramp up / down / cs
w25q128bv - 62 - 8.4 dc electrical characteristics parameter symbol conditions spec unit min typ max input capacitance c in ( 1 ) v in = 0v ( 1 ) 6 pf output capacitance cout ( 1 ) v out = 0v ( 1 ) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 6 50 a power - down current i cc 2 /cs = vcc, vin = gnd or vcc 1 .5 1 5 a current read data / dual /quad 1mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 4 / 5/6 6/7.5 /9 ma current read data / dual /quad 33mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 6/ 7/8 9/10.5/12 ma current read data / dual /quad 50mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 7 / 8/9 10/12/13.5 ma current read data / dual output read /quad output r ead 80mhz i cc 3 ( 2 ) c = 0.1 vcc / 0.9 vcc do = open 10 / 11/12 15/16.5/18 ma current write status register i cc 4 /cs = vcc 8 12 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i c c 7 /cs = vcc 20 25 ma input low voltage v il vcc x 0.3 v input high voltage v ih vcc x 0.7 v output low voltage v ol i ol = 1.6ma 0. 2 v output high voltage v oh i oh = C 100 a vcc C 0.2 v notes: 1 . tested on sample basis and specified through design and characterization data. ta = 25 c, vcc = 3 v. 2 . checker board pattern.
w25q128bv publication release date: october 03 , 201 3 - 63 - revision h 8.5 ac measurement conditions parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vcc to 0 .8 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0. 5 vcc to 0. 5 vcc v note: 1. output hi - z is defined as the point where data out is no longer driven. figure 3 9 . ac mea surement i/o waveform input and output timing reference levels input levels 0.8 vcc 0.2 vcc 0.5 vcc
w25q128bv - 64 - 8.6 ac electrical characteristics description symbol alt spec unit min typ max clock frequency for all single spi, dual output i nstructions except read data (03h) f r f c 1 d.c. 104 mhz clock frequency for dual i/o & quad spi instr uctions f r f c 2 d.c. 7 0 mhz clock frequency for read data instruction ( 03h ) f r f c 3 d.c. 33 mhz clock high, low time for all quad spi instructions t clh 1 , t cll 1 ( 1) 5 ns clock high, low time for single/dual instructions except read data (03h) t clh 1 , t c ll 1 ( 1) 4 ns clock high, low time for read data (03h) instruction t crlh , t crll ( 1) 8 ns clock rise time peak to peak t clch ( 2) 0.1 v/ns clock fall time peak to peak t chcl ( 2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk t chsh 5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect ti me (for array read ? array read) t shsl t csh 10 ns /cs deselect time t shsl t csh 50 ns output disable time t shqz ( 2) t dis 7 ns clock low to output valid t clqv t v 7 ns output hold time t clqx t ho 0 ns continued C next page
w25q128bv publication release date: october 03 , 201 3 - 65 - revision h 8.7 ac electrical char acteristics ( contd) description symbol alt spec unit min typ max /hold active setup time relative to clk t hlch 5 ns /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low - z t hhqx ( 2) t lz 7 ns /hold to output high - z t hlqz ( 2) t hz 12 ns write protect setup time before /cs low t whsl ( 3) 20 ns write protect hold time after /cs high t shwl ( 3) 100 ns /cs high to power - down mode t dp ( 2) 3 s /cs high to standby mode without electronic signature read t res 1 ( 2) 3 s /cs high to standby mode with electronic signature read t res 2 ( 2) 1.8 s /cs high to next instruction after suspend t sus ( 2) 20 s write status register time t w 10 15 ms byte program time (first byte) (4 ) t bp1 30 50 s additional byte program time (after first byte) (4 ) t bp2 2.5 12 s page program time t pp 0.7 3 ms sector erase time (4kb) t se 30 200 /400 (5) ms block erase time ( 32 kb) t be 1 120 800 ms block erase time (64kb) t be 2 150 1 ,000 ms chip erase time t ce 2 5 40 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. val ue guaranteed by design and/or characterization, not 100% tested in produ ction. 3. only applicable as a constraint for a write status register ins truction when srp [1:0]=( 0 ,1). 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes progra mmed . 5. max value t se with <50k cycles is 200ms and >50k & <100k cycles is 400ms.
w25q128bv - 66 - 8.8 serial output timing 8.9 serial input timing 8.10 /hold timing 8.11 /wp timing /cs clk io output tclqx tclqv tclqx tclqv tshqz tcll lsb out tclh msb out /cs clk io input tchsl msb in tslch tdvch tchdx tshch tchsh tclch tchcl lsb in tshsl /cs clk io output /hold tchhl thlch tchhh thhch thlqz thhqx io input /cs clk /wp twhsl tshwl io input write status register is allowed write status register is not allowed
w25q128bv publication release date: october 03 , 201 3 - 67 - revision h 9. package spec ification 9.1 8 - pad wson 8x6 - mm (package code e) symbol millimeters inches min nom max min nom max a 0.70 0.75 0.80 0.02 8 0.0 30 0.031 a1 0.00 0.02 0.05 0.000 0.00 1 0.00 2 b 0.35 0.40 0.48 0.01 4 0.01 6 0.01 9 c 0.19 0.20 0.25 0 .007 0.00 8 0.0 10 d 7.90 8.00 8.10 0.311 0.31 5 0.31 9 d2 4.60 4.65 4.70 0.181 0.183 0.185 e 5.90 6.00 6.10 0.232 0.236 0.240 e2 5.15 5.20 5.25 0.20 3 0.20 5 0.20 7 e 1.27 bsc 0.050 bsc l 0.45 0.50 0.55 0.01 8 0.0 20 0.02 2 y 0.00 --- 0.05 0 0.000 --- 0.00 2
w25q128bv - 68 - 9.2 16 - pin soic 300 - mil (package code f) symbol millimeters inches min nom max min nom max a 2.36 2.49 2.64 0.093 0.098 0.104 a1 0.10 --- 0.30 0.004 --- 0.012 a 2 --- 2.31 --- --- 0.091 --- b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.18 0.23 0.28 0.00 7 0.009 0.011 d 10.08 10.31 10.49 0.397 0.406 0.413 e 10.01 10.31 10.64 0.394 0.406 0.419 e 1 7.39 7.49 7.59 0.291 0.295 0.299 e (2) 1.27 bsc . 0.050 bsc . l 0. 38 0.81 1.27 0.015 0.032 0.050 y --- --- 0.076 --- --- 0.003 0 --- 8 0 --- 8 notes: 1. controlling dimensions: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. gauge plane detail a gauge plane detail a
w25q128bv publication release date: october 03 , 201 3 - 69 - revision h 9.3 24 - ball tfbga 8x6 - mm (package code b, 5x5 - 1 ball array) symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.010 0.012 0.014 a2 --- 0.85 --- --- 0.033 --- b 0.35 0.40 0.45 0.014 0.016 0.018 d 7.90 8.00 8.10 0.311 0.3 15 0.319 d1 4.00 bsc 0.157 bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e1 4.00 bsc 0.157 bsc se 1.00 typ 0.039 typ sd 1.00 typ 0.039 typ e 1.00 bsc 0.039 bsc note: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
w25q128bv - 70 - 9.4 24 - ball tfbga 8x6 - mm (package code c, 6x4 ball array) symbol millimeters inc hes min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.010 0.012 0.014 b 0.35 0.40 0.45 0.014 0.016 0.018 d 7.95 8.00 8.05 0.313 0.315 0.317 d1 5.00 bsc 0.197 bsc e 5.95 6.00 6.05 0.234 0.236 0.238 e1 3.00 bsc 0.118 bsc e 1. 00 bsc 0.039 bsc note: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
w25q128bv publication release date: october 03 , 201 3 - 71 - revision h 10. ordering information notes: 1. the w prefix and the temperature designator i are not included on the part marking. 2. standard bulk shipments are in tube (shape e). please specify alternate packing method, such as tape and reel (sh a pe t) or tray (shape s) , when placing orders. 3 . for shipments with otp feature enabled, please specify when placing orders. w = winbond 25 q = s pi flash serial flash memory w ith 4 kb sectors, dual /quad i/o 128b = 128m - bit v = 2.7v to 3.6v f = 16 - pin soic 300 - mil e = 8 - pad wson 8x6 - mm b = 5 x 5 - 1 ball tfbga 8x6 - mm c = 6x4 ball tfbga 8x6 - mm g = green package (lead - free, rohs compliant, halogen - free (tbba), antimony - oxide - free sb 2 o 3 ) p = green package with status register power lock - down & otp enable d (2) w ( 1) 25q 128b v x i (1) i = industrial ( - 40 c to +85c)
w25q128bv - 72 - 10.1 valid pa rt numbers and top side marking the following table provides the valid part numbers for the w25q128b v spiflash memory . please contact winbond for specific availability by density and package type. winbond spiflash memories use a 1 2 - digit product number for ordering. however, due to limited space, the top side marking on all packages use an abbreviated 10 - digit number. pa rt numbers for industrial grade temperature: package type density product number top side marking f soic - 16 300mil 12 8m - bit w25q128b v fig w25q128bvfip 25q 128 bvfg 25q 128 bvfp e wson - 8 8x6mm 128m - bit w25q128b veig w25q128bveip 25q128bveg 25q128bvep b (1) tfbga - 24 8x6mm 5x5 - 1 ball array 128m - bit w25q128bv b ig w25q128bv b ip 25q128bv b g 25q128bv b p c (1) tfbga - 24 8x6mm 6x4 ball array 128m - bit w25q128bvcig w25q128bvcip 25q128bvcg 25q128bvcp note: these package types are special order only, please contact winbond for more information.
w25q128bv publication release date: october 03 , 201 3 - 73 - revision h 11. revision history version date page description a 03/26/09 all new create preliminary b 05/22/09 45, 67 & 68 modified t sus description updated ordering information c 08/ 20 /09 65 & 66 5, 58 & 62 53 update d p ackage d iagram s updated maximum operation frequency corrected uid waveform d 07/08/10 68 - 69 5, 61, 65 50, 54 63 5, 9, 20, 55 - 57 5, 70 updated package diagrams updated maximum operatio n frequency corrected 90h & 9fh waveforms updated icc parameters added sfdp feature added automotive temperature e 0 4 / 0 1 /1 1 8, 71 - 73 , 22 - 68, 46 , 56 - 58 added tfbga package updated diagrams added /wp timing diagram updated suspend description update sfdp to jedec 1.0 removed preliminary designator f 07/11/11 56, 57 66 updated sfdp spec title to jesd216 updated tclh/tcll g 04/18 /12 56 8, 69 60, 71 - 72 referred to sfdp definition application note added tfbga 5x5 ball array package updated operating temperatur e grades h 03 / 10 /1 3 5 60 - 65 added tfbga package m od ified dc /ac electrical characteristics
w25q128bv - 74 - trademarks winbond and s piflash are trademarks of winbond electronics corporation . all other marks are the property of their respective owner. important notice w inbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation where in personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from suc h improper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described he rein at any time, without notice.

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